Many types of memory devices, for example core memories and semiconductor memories, comprise matrices of memory cells. Memory cells in a matrix are logically arranged in rows and orthogonal columns. A particular memory cell can therefore be addressed in such a matrix by specifying the address of the row and the address of the column in which the cell is located.
The trend in memory device manufacture is to increase their density and complexity while reducing their size. Paradoxically, such devices generally require more input and output signal terminals yet have less room for accommodating such terminals than earlier devices.
To avoid the necessity of having separate terminals on a memory device for both row-address leads and column-address leads, row addresses and column addresses may conveniently be input to a memory device on the same terminals in a time-multiplexed manner, i.e., sequentially, one address at a time. The multiplexed address signals are brought to the memory device over a bus whose leads attach to the address input terminals of the memory device.
Memory devices are made in various sizes in terms of the numbers of memory cells which they contain. Different-size memory devices require different-size addresses to uniquely address each of the memory cells. Therefore different-size address buses and multiplexing mechanisms are generally required to bring the addresses to the various memory devices.
In systems that utilize memory devices, it is often desirable to permit the use of any one of a number of sizes of memory devices. One reason for this is that the product lifetime of the system, such as a computer, may span a decade, while the interval between subsequent improvements in memory density due to technological advances may be only a couple of years. The increases in memory density typically bring about corresponding decreases in memory cost per bit, hence the use of latest technology memories with existing systems is economically justifiable and desirable.
One way of achieving the capability of using different size memories in a system is to change the address bus and the bus-multiplexing mechanism each time a memory device of a different size is used in such a system. However, this approach is impractical because of the time, expense, and skill required for such change.
A second approach to enabling use of memory devices of various sizes in such systems is to equip the systems with address buses and bus-multiplexing mechanisms adapted for use with the largest memory devices that can be used in the system, and providing along therewith adaptive circuitry that selectively modifies the operation of these buses and multiplexing mechanisms to adapt them for use with smaller memory devices. However, the adaptive circuitry adds to the size and cost of the system. The adaptive circuitry also dissipates power, and hence it requires the use of larger and more expensive power supplies and larger and more expensive cooling systems. And the circuitry adds a delay to signals propagating between the memory and devices communicating therewith, thereby slowing down the operation of the system and adversely affecting system performance. Furthermore, adaptive circuitry quickly becomes extensive and complex with increases in the number of sizes of memory devices that it is to handle. Thus the adaptive circuitry can add significantly to the size, cost, and complexity of storage systems while at the same time decreasing their performance.